Video and text display

ABSTRACT

A display apparatus comprises a signal converter (SC) which converts input text information (IT) and interlaced input video information (IV) with a number of video lines (Li) in a video field (Fi) into a display signal (DS) which comprises display text (Ti) and display video (Vi). An addressing circuit (AD) addresses a display screen (DSC) of the display apparatus in successive non-interlaced display fields (Fi) which have a duration substantially equal to the video field (Fi) and a number of display lines (DLi) which is substantially twice the number of video lines (Li). The signal converter (SC) has an output to supply the display signal (DS) in which the display video (Vi) is present on odd or even display lines (DLi) only, in respective successive display fields (Fi), and in which the display text (Ti) is present on same display lines (DLi) of the successive display fields (Fi).

The invention relates to a display apparatus with a signal converter forconverting input text information and interlaced input video informationinto a display signal, such a signal converter, and a method ofconverting a signal.

U.S. Pat. No. 5,109,279 discloses a circuit for displaying TXT data asan auxiliary image which is superposed on a TV picture. The auxiliaryimage may cover ¼ or ½ of a display screen of a CRT. The TV picture isthe standard TV signal which is displayed in an interlaced manner. TheTXT signal is displayed in a non-interlaced manner by displayingsuccessively a first and a second field of the TXT signal only. This hasthe drawback that the TXT picture is susceptible to large area flickerand to movement artifacts.

It is an object of the invention to provide a display apparatus suitableto display video information in an interlaced manner and textinformation in a non-interlaced manner with less large area flicker.

To this end, a first aspect of the invention provides a displayapparatus as claimed in claim 1. A second aspect of the inventionprovides a signal converter as claimed in claim 10. A third aspect ofthe invention provides a method of converting as claimed in claim 11.Advantageous embodiments are defined in the dependent claims.

The display apparatus has a display screen on which a display signal isdisplayed. The display signal comprises the display video which isoptimally displayed in an interlaced manner, and the display text whichis optimally displayed in a non-interlaced manner. The video informationis received as interlaced input video information which has video fieldsof video lines. The video lines of successive fields comprise interlacedvideo information.

The display screen is addressed by the addressing circuit to displaynon-interlaced display fields of display lines. The display fields havea substantially same duration as the video fields and a number ofdisplay lines which is substantially twice the number of video lines.

The signal converter supplies the display signal which comprises, insuccessive display fields: the display video alternatively on odd oreven display lines only, and the display text on same display lines ofsaid successive display fields.

By using, in successive display fields, only halve of the availabledisplay lines which are displaced by one line, the video information isdisplayed in an interlaced manner again. The text information isdisplayed in every display field on the same lines and thus isrepresented in a non-interlaced manner.

As an example, the video information may be a television broadcastsignal such as NTSC or PAL, and the text signal may be a teletext or anOSD (on screen display) signal. The PAL television signal comprises aframe of 625 lines which forms a complete picture and which is composedof a so called odd and even field which have lines that interlace. Theodd field comprises the 312½ odd lines of the picture, the even fieldcomprises the 312½ even lines of the picture. If the video signal is aPAL television signal, the display fields have the same 50 Hz repetitionfrequency as the video fields and 625 lines instead of 312½ lines. The625 lines of successive display fields are displayed in a non-interlacedmanner, and thus overlap each other.

During a particular display field, the odd input video lines aredisplayed on the odd display lines, during the next display field, theeven input video lines are displayed on the even display lines and soon. In all display fields, the text information is displayed on the odddisplay lines only, or on the even display lines only, or on all displaylines if the text information is generated with the same number of linesas the number of (visible) display lines.

The text information may be displayed over the display video therebyobscuring the displayed video. Preferably, the display video iscompressed to cover only a part of the display screen. The textinformation is displayed on the remaining part of the display screen.

In an embodiment claimed in claim 2, the signal converter comprises amemory and a clock generator. The clock generator supplies a write clockto the memory to store the input video information in the memory, and aread clock to read the display video from the memory. The read clock hasa repetition frequency which is at least two times higher than therepetition frequency of the write clock. A read clock with twice thefrequency of the write clock is required to convert an input video lineinto a display video line which has a duration which is halve theduration of the input video line. If the display video has to becompressed to cover only a part of the display screen, the read clockmay have a frequency higher than twice the frequency of the write clock.

In an embodiment claimed in claim 8, if the video information isdisplayed on the first halve of the display screen and the textinformation on the second halve of the display screen (or the other wayaround), the stored video information should be read with a read clockwhich is four times the write clock. The text generator should becontrolled to supply its text information during the period of time theremaining halve of the display screen is not used to display the videoinformation.

In this manner, the video information and the text information aredisplayed besides each other and can be watched in complete, which isnot the case when the text information obscures the video information asoccurs with PIP. This feature is especially relevant if the displayscreen has a 16 to 9 aspect ratio.

Alternatively, it is possible to use a memory to compress both the videoinformation and the text information. The input video information andthe text information are stored line by line in the line memory. Thecontrolling circuit controls the storing of the video information andthe text information in the line memory and the reading of the data fromthe line memory such that in successive display fields the videoinformation is alternatively displayed on odd or even lines only, andthe text information is displayed on the same lines.

Alternatively, the compression of the video information and ifapplicable, the text information may be obtained by skipping samples.

It is also possible to superpose the text information on the videoinformation in a same manner as known from PIP (Picture In Picture).

In an embodiment claimed in claim 3, the lines of the video informationare displayed in a predetermined display field on the odd lines only bysupplying the read clock to the memory during the odd lines only. In thenext display field, the lines of the video information are displayed onthe even lines only by supplying the read clock to the memory during theeven lines only.

In an embodiment claimed in claim 4, the controller controls the textgenerator to supply the text information to the same display lines ofsuccessive display fields to obtain a non-interlaced display of the textinformation.

Usually, the text generator comprises a memory in which the textinformation to be displayed is stored. The instant of reading the datamay be controlled by controlling a read clock of this memory.

In an embodiment claimed in claim 5, the lines of the text informationare displayed on either the odd or the even display lines of successivedisplay fields. This has the advantage that a common available textgenerator can be used. The text generator only needs to be able toprovide text information for halve of the display lines at at leasttwice the rate.

In an embodiment claimed in claim 6, the text information is displayedon all (visible) lines of the display fields. This improves the qualityof the display of the text information, but requires a text generatorable to generate the text information for all (visible) display lines.

In an embodiment as claimed in claim 7, the display lines or parts ofthe display lines on which no video and no text information is displayedare filled in with black level. The filling in of the black level may beobtained by blanking.

For the area of the display screen where the interlaced video isdisplayed, the line parts to be filled in are in the odd lines when thevideo information is displayed on the even lines, or the even lines whenthe video information is displayed on the odd lines. For the area of thedisplay screen where the text information is displayed, if the textinformation is displayed on the even lines only, always the odd linesare blanked, if the text information is displayed on the odd lines only,always the even lines are blanked. If the text information is displayedon all the lines, no lines have to be blanked.

These and other aspects of the invention are apparent from and will beelucidated with reference to the embodiments described hereinafter.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 shows a block diagram of a display apparatus in accordance withthe invention,

FIG. 2 shows a timing overview to elucidate the video lines and fieldsof the input video information, and the display lines and display fieldsof the display signal,

FIG. 3 show the information displayed on display lines of twoconsecutive display fields in an embodiment in accordance with theinvention, and

FIG. 4 shows a block diagram of an embodiment of the signal converter inaccordance with the invention.

The same references in different Figures denote the same elements orsignals which have the same function. References indicated by a capitalletter followed by an indices i refer to one or more elements or signalswhich are indicated by the same capital letter and a number instead ofthe i, such references also refer to elements or signal which areindicated by the same capital letter followed by one or moreapostrophes.

FIG. 1 shows a block diagram of a display apparatus in accordance withthe invention. The display apparatus comprises a signal converter SC, adisplay screen DSC and an addressing circuit AD. The signal converter SCreceives the input video information or signal IV and the input textinformation or signal IT to supply the display signal DS to the displayscreen DSC of a display device. The addressing circuit AD receivessynchronization information SI belonging to the input video informationIV and supplies addressing information AS to the display device.

The input video signal IV may be a standard television broadcastbaseband signal such as the R, G, and B signal, or a CVBS signal. Thesynchronization information SI may comprise the horizontal and verticalsynchronization pulses. The input text information IT may be generatedby a teletext decoder or an On Screen Display (OSD) circuit. The displaydevice may be a Cathode Ray Tube (CRT) or a matrix display such as aLiquid Crystal Display (LCD) or a Plasma Display Panel (PDP). Theaddressing circuit AS comprises a horizontal and vertical deflection ifthe display device is a CRT, or row and column drivers if the displaydevice is a matrix display.

The addressing circuit AD drives the display device such that in a videofield period Fi (see FIG. 2: F1, F2, F1′) of the input video signal IVthe number of display lines DLi (DL1, DL2, DL3; DL1′, DL2′, DL3′, DL4′;DL1″, DL2″, DL3″) is the double of the number of video lines Li (L1, L2,L1′, L2′, L1″, L2″) of the video field period Fi. The consecutivedisplay fields Fi are displayed in a non-interlacing manner. Such adrive of a display device is known as progressive scan. However, theinformation displayed on the progressive scanned display device inaccordance with the invention is different from the prior art. In theprior art progressive scanned display devices, the input videoinformation IV is processed to be displayed on all display lines DLi. Inthe progressive scanned display device in accordance with the invention,the input video information IV is displayed on half of the display linesDLi of a display field Fi only.

FIG. 2 shows a timing overview to elucidate from top to bottom in theorder mentioned: the fields Fi of the input video information IV, whichare equal to the fields Fi of the display signal DS, the lines Li of theinput video information IV, the display lines DLi of the display fieldsFi, and the display signal DS. The display signal DS comprises displayvideo Vi and display text Ti and information B where no display video Viand no display text Ti is displayed.

Of the fields Fi the successive fields F1, F2 and F1′ are shown. Withrespect to the input video information IV, for example, the fields F1and F1′ are odd fields which comprise the odd video lines L1, L2, . . .and L1″, L2″, . . . . The field F2 is an even field and comprises theeven video lines L1′, L2′, . . . . The odd and even fields Fi compriseinterlaced video information, and thus are intended to be displayed oninterlacing display lines DLi.

With respect to the display signal DS, all the fields Fi comprisedisplay lines DLi which are displayed in a non-interlaced manner:display line DL1 of the display field F1 is displayed on the sameposition on the display screen as the display line DL1′ of the displayfield F2, and so on for all display lines DLi with the same indices i.The number of display lines DLi in a field Fi is the double of thenumber of video lines in the field Fi. By way of example, FIG. 2 showsthe display signal DS when the input video signal IV is displayed asdisplay video Vi on the left halve of the display screen DSC, and theinput text information IT as display text information Ti on the righthalve of the display screen DSC.

The display signal DS shows that during the field F1, the input videoinformation IV of the video line L1 is displayed on the first halve ofthe display line DL1 as the display video V1. The corresponding line T1of the display text Ti is displayed on the last halve of the displayline DL1. On the second display line DL2 of the field F1, no displayvideo or text information is displayed and a black level B is inserted.The input video information IV of video line L2 is displayed on thefirst halve of the display line DL3 as the display video V2. Thecorresponding line T2 of the display text Ti is displayed on the lasthalve of the display line DL3. And so on during the rest of field F1. Asame order of data and signals occurs in the all the odd fields F1, F1′,. . . .

The display signal DS shows that during the field F2, the input videoinformation IV of video line L1′ is displayed on the first halve of thedisplay line DL2′ as the display video V1′. The corresponding line T1′of the display text Ti is displayed on the last halve of the displayline DL1. On the first halve of the display line DL1 and the last halveof the display line DL2 of the field F2, no information is displayed andthe black level B is inserted. The input video information IV of videoline L2′ is displayed on the first halve of the display line DL4′ as thedisplay video V2′. The corresponding line T2′ of the display text Ti isdisplayed on the last halve of the display line DL3′. And so on duringthe rest of field F2. A same order of data and signals occurs in the allthe even fields F2, . . . .

FIG. 2 illustrates that the input video information IV is displayed inan interlaced manner: during the odd fields F1, F1′, . . . the video isdisplayed as display video V1, V1″, . . . on the odd display lines DL1,DL1″, while during the even fields F2, . . . the video is displayed asdisplay video V1, . . . on the even display lines DL2′, DL4′ . . . .

The display text lines Ti are displayed on the same display lines DLi(in this example, the odd lines) in all the fields Fi, and thus aredisplayed in a non-interlaced manner.

It has to be noted that FIG. 2 only serves as an example of a possibleway to display the input video information IV on non-interlaced displaylines DLi in an interlaced manner and to display the input textinformation in a non-interlaced manner. Relevant is that successivefields Fi of the input video information IV are displayed in successivefields Fi alternating on the even display lines DLi or the odd displaylines DLi. While the text information is displayed in a non-interlacedmanner by supplying the display text information Ti on the same displaylines DLi in all the display fields Fi.

FIGS. 3A and 3B show the information displayed on display lines of twoconsecutive display fields. FIG. 3A shows the information displayed onsix consecutive lines DL1 to DL6 of the field F1, and FIG. 3B shows theinformation displayed on the corresponding six consecutive lines DL1′ toDL6′ of the next field F2.

By way of example, FIG. 3 shows the displayed information on the displayscreen DSC when the input video signal IV is displayed as display videoVi on the left halve of the display screen DSC, and the input textinformation IT as display text information Ti on the right halve of thedisplay screen DSC.

The display lines DLi or the parts (which in this example are halvedisplay lines DLi) of the display lines DLi on which no videoinformation and no text information is displayed are presented in black.

During the field F1, the display video V1, V2, V3, . . . is displayed onthe left halve of the odd display lines DL1, DL3, DL5, . . . . Thedisplay text T1, T2, T3, . . . is displayed on the right halve of theodd display lines DL1, DL3, DL5, . . . . No information is displayed onthe even display lines DL2, DL4, DL6, . . . .

During the field F2, the display video V1′, V2′, V3′, . . . is displayedon the left halve of the even display lines DL2′, DL4′, DL6′, . . . .The display text T1′, T2′, T3′, . . . . is still displayed on the righthalve of the odd display lines DL1, DL3, DL5, . . . . No information isdisplayed on the left halve of the odd display lines DL1, DL3, DL5, . .. and on the right halve of the even display lines DL2, DL4, DL6, . . ..

Consequently, the display video Vi is displayed in an interlaced mannerand the text information is displayed in a non-interlaced manner.

FIG. 4 shows a block diagram of an embodiment of the signal converter inaccordance with the invention.

The analog to digital converter ADC receives an analog input videosignal IV which may be a baseband TV signal, and supplies a digitalinput video signal DIV to the switch S1. The analog to digital converterADC can be omitted if the input video IV signal is received in digitalform. The switch S1 supplies the digital input signal to the line memoryLM1 or to the line memory LM2. A switch S2 supplies the display video DVby selecting either the output of the line memory LM1, the output of theline memory LM2, or the black level signal BL supplied by the blacklevel generator BG. The adder ADD adds the text information TI to thedisplay video DV to obtain the display signal DS. The digital to analogconverter DAC converts the digital display signal DS into an analogdisplay signal DSA which is supplied to the display device DSC.

The addressing circuit DA receives synchronization information SIbelonging to the input video information IV and addresses the displaydevice DSC to provide in a display field Fi a number of display linesDLi that is twice the number of the video lines Li of the input videoinformation IV. The display field Fi has the same duration as the fieldFi of the input information IV. The synchronization information SIcomprises the horizontal and vertical synchronization information. Theaddressing circuit DA may be the known addressing circuit used inprogressive scan display apparatuses.

A clock generator CG generates a write clock CLK1 and a read clock CLK2.The clock generator CG may be a known line phase locked loop whichreceives the synchronization information SI to lock the clock signalsCLK1 and CLK2 to the line synchronization pulses. The write clock CLK1is supplied to the analog to digital converter ADC. The read clock CLK2is supplied to the digital to analog converter DAC.

The line memory LM1 has a clock input which receives the write clockCLK1 or the read clock CLK2 via the switch S3. The line memory LM2 has aclock input which receives the write clock CLK1 or the read clock CLK2via the switch S4.

A controller CO receives the synchronization information SI and suppliesthe control signal CS1 to the switches S1, S3 and S4, the control signalCS2 to the switch S2 and the control signal CS3 to the text generatorTG.

To elucidate the operation of the signal converter SC, the startingsituation is defined by the controller CO which commands the switches S1to S4 to take the positions shown in FIG. 4. The write clock CLK1 issupplied to the line memory LM2 to write a line Li of the input video IVinto this memory LM2. During this video line Li the read clock CLK2 issupplied to the line memory LM1 to read a previously stored line Li fromthis memory LM1. In a next video line Li, the switches S1 to S4 take theopposite positions and the video information stored in the memory LM2during the preceding video line Li is read while the present video lineLi is stored in the memory LM1.

Two situations are discussed, in the first situation, the input videoinformation IV is displayed full screen, in the second situation, theinput video information IV is displayed on the left halve of the displayscreen DS.

In the first situation, the read clock CLK2 has a frequency which istwice the frequency of the write clock CLK1. The switch S2 is connectedto the line memory LM2 when a stored video line Li is read from thismemory LM2. The switch S2 is connected to the line memory LM1 when astored video line Li is read from this memory LM1. The switch S2 isconnected to the black level generator BG when no information is readfrom both the memory LM1 and the memory LM2. If the text generator TG iscontrolled by the control signal CS3 to display text Ti, this displaytext Ti will cover or mix with the display video information DV. Thedisplay video information DV is covered when in the area where the textTi is displayed, the text Ti is displayed on all display lines DLi, orwhen the display lines DLi between the text lines are blanked.

In the second situation, the read clock CLK2 has a frequency which isfour times the frequency of the write clock CLK1. For the explanation ofthe operation of the signal converter SC the lines DL1 to DL4 shown inFIG. 3A, and the lines DL1′ to DL4′ shown in FIG. 3B will be discussed.

With reference to FIG. 3A, it is assumed that the line DL1 is read fromthe memory LM1. All the switches S1 to S4 are in the position shown inFIG. 4. The stored video line Li which comprises the video informationV1 is read from the line memory LM1 at four times the rate at which thisvideo line is written into the memory LM1. For example, the write clockCLK1 has a frequency of 13.5 MHz and the read clock CLK2 has a frequencyof 54 MHz. Consequently, the video information V1 is displayed in thefirst have of the display line DL1. The control signal CS3 instructs thetext generator TG to display a line of the text information IT duringthe second halve of the display line DL1. In the next display line DL2,the switch S2 is put in the middle position and a black line isdisplayed. The video information V2 of the present video line is storedin the memory LM2 during the display lines DL1 and DL2.

During the first halve of the display line DL3, the switches S1 to S4are in the opposite positions to read the video information V2 out ofthe memory LM2. The control signal CS3 instructs the text generator TGto display a line of the text information IT during the second halve ofthe display line DL3. In the next display line DL4, the switch S2 is putin the middle position and a black line is displayed.

This sequence is repeated for every block of four adjacent display linesDLi.

With reference to FIG. 3B, it is assumed that the line DL1′ is read fromthe memory LM1. All the switches S1 to S3 are in the position shown inFIG. 4. During the first halve of the display line DL1′, the switch S2is in the middle position to supply black information. During the secondhalve of the display line DL1′, the control signal CS3 instructs thetext generator TG to display a line of the text information IF. Duringthe first halve of the display line DL2′, the switch S2 is in the lowerposition to read the information out of the memory LM1 to display thevideo information V1′. During the second halve of the display line DL2′,the switch S2 is in the middle position to supply black information. Thevideo information V2′ of the present video line is stored in the memoryLM2 during the display lines DL1′ and DL2′.

During the first halve of the display line DL3′, the switches S1 to S3are in the opposite positions to enable to read the video information V2out of the memory LM2, and the switch S2 is in the middle position tosupply black information. During the second halve of the display lineDL3′, the control signal CS3 instructs the text generator TG to displaya line of the text information IT. During the first halve of the displayline DL4′, the switch S2 is in the upper position to read theinformation out of the memory LM2 to display the video information V2′.During the second halve of the display line DL2′, the switch S2 is inthe middle position to supply black information.

This sequence is repeated for every block of four adjacent display linesDli′.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. For example, the black level generatorBG and the middle position of the switch S2 may be omitted. Theinsertion of the black information BL may be obtained via a blankinginput of a RGB processor (available as integrated circuit) positionedbetween the digital to analog converter DAC and the display device DSC.The adder ADD may be part of the RGB processor.

Instead of inserting the black level, it is possible to repeat the videoor text information of a previous line.

Instead of the switches S1 and S2 it is possible to arrange the memoriesLM1 and LM2 in parallel between the converter ADC and the adder ADD. Theline memories LM1 and LM2 are controlled via a read/write input toselect between storing or reading information. The read clock signalCLK2 is halted after the stored information is read from the line memoryLM1 or LM2 during the appropriate period in time.

In the claims, any reference signs placed between parenthesis shall notbe construed as limiting the claim. The word “comprising” does notexclude the presence of other elements or steps than those listed in aclaim. The word “a” or “an” preceding an element does not exclude thepresence of a plurality of such elements. The invention can beimplemented by means of hardware comprising several distinct elements,and by means of a suitably programmed computer. In the device claimenumerating several means, several of these means can be embodied by oneand the same item of hardware. The mere fact that certain measures arerecited in mutually different dependent claims does not indicate that acombination of these measures cannot be used to advantage.

To summarize, the invention is directed to a display apparatus whichcomprises a signal converter SC which converts input text information ITand interlaced input video information IV with a number of video linesLi in a video field Fi into a display signal DS which comprises displaytext Ti and display video Vi. An addressing circuit AD addresses adisplay screen DSC of the display apparatus in successivenon-interlacing display fields Fi which have a duration substantiallyequal to the video field Fi and a number of display lines DLi which issubstantially twice the number of video lines Li. The signal converterSC has an output to supply the display signal DS in which the displayvideo Vi is present on odd or even display lines DLi only, in respectivesuccessive display fields Fi, and in which the display text Ti ispresent on same display lines DLi of the successive display fields Fi.

1. A display apparatus comprising: a signal converter for convertinginput text information and interlaced input video information having anumber of video lines in a video field into a display signal (DS)comprising display text and display video, and addressing means foraddressing a display screen of the display apparatus in successivenon-interlaced display fields having a substantially same duration asthe video field and a number of display lines being substantially twicethe number of video lines, wherein the signal converter has an outputfor supplying the display signal in which the display video is presenton odd or even display lines only in respective successive displayfields, and in which the display text is present on same display linesof the successive display fields.
 2. A display apparatus as claimed inclaim 1, wherein the signal converter comprises a memory and a clockgenerator for supplying a write clock to the memory to store said inputvideo information in the memory, and for supplying a read clock to thememory to read the display video from the memory, wherein the read clockhas a repetition frequency which is at least two times higher than arepetition frequency of the write clock.
 3. A display apparatus asclaimed in claim 2, wherein the signal converter further comprises acontroller for controlling the clock generator to supply the read clockonly during odd display lines of a predetermined display field and onlyduring even lines of a successive display field.
 4. A display apparatusas claimed in claim 1, wherein the display apparatus comprises a textgenerator for supplying the input text information being the displaytext, and the signal converter comprises a controller for controllingthe text generator to supply the display text on same lines of saidsuccessive display fields.
 5. A display apparatus as claimed in claim 4,wherein the text generator has an input for receiving timing informationfrom the controller to supply the display text on either the odd or theeven lines of the display fields.
 6. A display apparatus as claimed inclaim 4, wherein the text generator has an input for receiving timinginformation from the controller to supply the display text onsubstantially all the lines of the display fields.
 7. A displayapparatus as claimed in claim 1, wherein the display apparatus furthercomprises means for supplying a black-level to the display lines or partof the display lines on which no display video or no display text isdisplayed.
 8. A display apparatus as claimed in claim 2, wherein thedisplay apparatus comprises a text generator for supplying the inputtext information being the display text, and the signal convertercomprises a controller for controlling the text generator to supply thedisplay text on same lines of said successive display fields, whereinthe repetition frequency of the read clock is four times the repetitionfrequency of the write clock, and wherein the controller is adapted forcontrolling the memory to supply the display video on either a left orright halve of the display screen, and for controlling the textgenerator to supply the display text on a remaining halve of the displayscreen.
 9. A display apparatus as claimed in claim 2, wherein the memorycomprises two line memories for storing data of a predetermined one ofthe video lines in one of the two line memories, and reading the displayvideo of a preceding video line from the other line memory.
 10. A signalconverter for converting input text information and interlaced inputvideo information having a number of video lines in a video field into adisplay signal suitable for display on a display screen of a displayapparatus being addressed in successive non-interlaced display fieldshaving a substantially same duration as the video field and a number ofdisplay lines being substantially twice the number of video lines, thedisplay signal comprising display text and display video, the signalconverter having an output for supplying the display signal comprising,in successive display fields, the display video alternatively on odd oreven display lines only, and the display text on same display lines ofsaid successive display fields.
 11. A method of converting input textinformation and interlaced input video information having a number ofvideo lines in a video field into a display signal comprising displaytext and display video, the method comprising addressing a displayscreen of a display apparatus in successive non-interlaced displayfields having a substantially same duration as the video field and anumber of display lines being substantially twice the number of videolines, supplying, in successive display fields, the display videoalternatively on odd or even display lines only, and for supplying thedisplay text on same display lines of said successive display fields.